1. Field of Invention
This invention relates to the field of digital comparators, particularly bit and word comparators such as are used to perform comparisons between pairs of addresses or data words in computing environments.
2. Discussion of Related Art
In many digital computing environments, there is a recurring need to perform “wide” (i.e., multi-bit) comparisons of two or more digital values. Often, these values represent addresses or information or instructions in a memory. Typically, the width of such values is that of a digital word in the system, and sometimes multiple words. Speed is usually important as the result of the comparison will determine subsequent processing to be performed and that processing will have to be held in abeyance until the result of the comparison is known. For example, the comparison may determine whether an addressed data block is already in a cache memory (from which fast retrieval is possible) or whether it need be fetched from a different, slower memory subsystem. Therefore, instead of performing the comparison one bit at a time, it is common practice to perform a full word comparison at one time. That is, each pair of corresponding bits is bit-wise compared and the results of the bit-wise comparisons are combined in such a way that a mismatch in any bit position will signal a mismatch at the word level.
Not only is speed an important consideration for such “word” comparators, but also in many applications, such as those involving portable computing or communications devices, so is power consumption.
FIG. 1 depicts a typical prior art circuit 100 for performing one of the bit-wise comparisons. For purposes of providing a context, it shall be assumed that the words being compared represent addresses in a computing system memory structure, though they could have other significance (e.g., the contents of those addresses). The comparison is made between a first address (word) and a second address (word). Corresponding bits are compared one at a time, using a circuit such as 100 for each of those comparisons.
A first address bit CMPADR is received on line and a second address bit DAGADR is received on line 104. Inverters 106, 108, 110 buffer the input of the CMPADR bit and provide to the circuit 100 a true value of that bit on line 112 and a complement, or inverted, value on line 114. The sources of pass transistors 116 and 118 receive those true and complement values and their drains connect to the set and reset inputs of a strobed latch 120. The signal LDCMP applied at terminal 122 strobes the pass transistors 116 and 118 when the CMPADR address bit is in a known, reliable condition, to set or reset the latch 120.
Inverter 124 provides a complement value for the DAGADR bit and the true and complement values of the DAGADR bit are supplied to one input of each of the two NAND gates 126, 128. The other input to each of those NAND gates is a clock signal, CLK. Thus, when the CLK signal is high, the outputs of inverters 132, 134 is a buffered version of the true and complemented values of the DAGADR bit, respectively.
The four pass transistors 142, 144, 146, 148 constitute an exclusive-OR (X-OR) gate which then performs a digital differential comparison of the true and complement values on the respective nodes 152, 154 and 156, 158; if there is a mismatch, then node 160, which has been pre-charged, is pulled low. Sensing logic 170 provides a signal MATCH at node 180.
The approach of FIG. 1, while usable, exhibits certain less than ideal characteristics. For example, the comparison must be disabled while the comparison node 160 is pre-charged, imposing a speed restriction. An additional speed restriction comes from the fact that the X-OR gate comprises four transistors, having a portion of their capacitance that has to be discharged when the comparison node 160 is pulled low, and having to be charged when that node is pre-charged, where this portion is determined by the state of latch 120 and its affect on the “on/off” state of transistors 144 and 148. Further, noise margins are compromised by the fact that some nodes coupled to the comparison node 160, specifically nodes 152 and 154, will in practice not be completely pre-charged. This is due to the large amount of time required to completely pre-charge nodes 152 and 154 through their associated NMOS transistors 148 and 144, so in practice the pre-charge is typically left incomplete and chosen based on a point of diminishing return. The pre-charge on nodes 152 and 154 is also further degraded if the state held by latch 120 changes during the pre-charging of the comparison node, as this results in less time to properly pre-charge nodes 152 and 154.
Accordingly, a need exists for an improved word comparator which is capable of higher speed operation and better noise margins, and which consumes less power.